There are many types of non-volatile memory cells, such as floating gate cells and NROM (nitride read only memory) or MirrorBit cells, all of which store charge in a storage layer of the cell which overlays an active channel of the cell.
An exemplary NROM cell is shown in FIG. 1, to which reference is now made. The active channel of the cell, labeled 10, lies between two junction bit lines 12. Above channel 10 is the storage layer, labeled 14, which, for NROM cells, is comprised of an oxide-nitride-oxide sandwich. Running perpendicularly to bit lines 12 is a word line 16, formed of polysilicon. In the NROM cell, the charge is stored in the nitride layer of ONO sandwich 14. An insulator 15 is placed on top of bit line 12 to avoid electrical shorts between bit lines and word lines.
Storage layer 14 affects the activity of the channel. If the layer is charged, no current can flow through channel 10 while if the storage layer is not charged, current can flow. By measuring the current through channel 10 of a particular cell, the data stored therein (defined by the presence or absence of charge) may be read.
The cell shown in FIG. 1 can store two physically separated packs of charges, labeled 5 and 6, thus enabling two digital bits per one cell. To program bit 6 for example, the channel hot electron (CHE) mechanism is invoked by applying 0V on bit line 12a, 3-6V on bit line 12b and 5-10V on word line 16. Electrons travelling in channel 10, from bit line 12a to bit line 12b, heat up (i.e. collect kinetic energy), particularly in the vicinity of bit line 12b. Some of the electrons are scattered, causing them to be injected into trapping layer 14 at the location of bit 6. To program bit 5, the voltages provided to bit lines 12a and 12b are exchanged.